Apparatus and methods for adjusting performance characteristics of programmable logic devices

ABSTRACT

A programmable logic device (PLD) includes a circuit that controls a supply voltage of at least a portion of the circuitry within the PLD (such as a block, a sub-block, or a region). The circuit also filters noise within the PLD. Controlling the supply voltage allows trading off various performance characteristics, such as speed and power consumption.

TECHNICAL FIELD

The inventive concepts relate generally to adjusting the performance ofprogrammable logic devices (PLDs). More particularly, the inventionconcerns adjusting the supply voltage/power consumption of PLDs, as wellas noise reduction and isolation in PLDs.

BACKGROUND

PLDs are ubiquitous electronic devices that provide flexibility to notonly designers, but also end-users. During the design cycle of anelectronic circuit or system, a designer may perform a relatively largenumber of design iterations by simply re-programming the PLD for eachdesign. Thus, the length and expense of the design cycle decreasescompared to other alternatives. Similarly, the end-user may have adesired level of control over the functionality of a design thatincludes PLD(s). By programming the PLD(s) in the field or even on areal-time basis, the user can change the way the circuit or systembehaves.

To accommodate increasingly complex designs, modern PLDs include arelatively large number of transistors. Furthermore, users demand everhigher performance, which results in larger operating frequencies.Consequently, the power consumption, power dissipation, die temperaturesand, hence, power density (power dissipation in various circuits orblocks), of PLDs has tended to increase. The upward march of the powerdensity, however, may make PLDs design and implementation impractical orfailure-prone. A need exists for PLDs that feature adjustableperformance, such as adjustable power consumption in various PLD blocksand circuits.

SUMMARY

The disclosed novel concepts relate to apparatus and methods foradjusting the performance of PLDs, including adjusting the supplyvoltage/power consumption of PLDs, as well as noise reduction andisolation in PLDs. One aspect of the invention relates to apparatus foradjusting the performance of PLDs. In one embodiment, a PLD includes acircuit that controls a supply voltage of another circuit within thePLD. The controlling circuit further filters noise within the PLD.

In another embodiment, a PLD includes a circuit that resides in a deepn-well in the PLD. The circuit in the deep n-well couples to a variableimpedance device. The variable impedance device adjusts the supplyvoltage of the circuit in the deep n-well, thus adjusting itsperformance.

Another aspect of the invention relates to methods of configuring,operating, and adjusting the performance of PLDs. In one embodiment, amethod of configuring a PLD to implement an electronic circuit includesmapping the electronic circuit to functional resources within the PLD togenerate a circuit to be implemented by the PLD. The method furtherincludes identifying at least one critical circuit path in the circuitto be implemented by the PLD, and setting the supply voltage level of atleast a portion of the critical circuit path.

In another embodiment, a method of operating a PLD includes setting thesupply voltage level of a circuit in the PLD to a voltage level, anddetermining whether a performance measure of the PLD meets a particularcriterion. The method further includes adjusting the supply voltagelevel of the circuit depending on whether the performance measure of thePLD meets the criterion.

Another embodiment relates to a method of operating a PLD that isconfigured to function in a desired or prescribed operating environment.More specifically, the method includes setting the supply voltage levelof a circuit in the PLD to a voltage level, and adjusting the supplyvoltage level of the first circuit depending on at least onecharacteristic of the operating environment of the programmable logicdevice (PLD).

BRIEF DESCRIPTION OF THE DRAWINGS

The appended drawings illustrate only exemplary embodiments of theinvention and therefore should not be considered as limiting its scope.Persons of ordinary skill in the art who have the benefit of thedescription of the invention appreciate that the disclosed inventiveconcepts lend themselves to other equally effective embodiments. In thedrawings, the same numeral designators used in more than one drawingdenote the same, similar, or equivalent functionality, components, orblocks.

FIG. 1 shows a general block diagram of a PLD according to anillustrative embodiment of the invention.

FIG. 2 illustrates a floor-plan of a PLD according to an exemplaryembodiment of the invention.

FIG. 3 depicts a block diagram of an exemplary embodiment ofprogrammable logic in a PLD according to the invention.

FIG. 4 shows a circuit arrangement for adjusting the supply voltage of adesired circuit in a PLD according to an exemplary embodiment of theinvention.

FIG. 5 illustrates another circuit arrangement for adjusting the supplyvoltage of a desired circuit in a PLD according to an exemplaryembodiment of the invention.

FIG. 6 depicts a circuit arrangement for reducing the noise level in aPLD according to an exemplary embodiment of the invention.

FIG. 7 shows another circuit arrangement for reducing the noise level ina PLD according to an exemplary embodiment of the invention.

FIG. 8 illustrates an arrangement for providing a flexible mechanism foradjusting the performance of the various parts of a PLD according to anexemplary embodiment of the invention.

FIGS. 9A-9C depict circuit arrangements for distributing and generatingpower supply voltages in PLDs according to exemplary embodiments of theinvention.

FIG. 10 shows an example of using n-wells to isolate noise-sensitivecircuits in a PLD according to an illustrative embodiment of theinvention.

FIG. 11 illustrates various software modules that PLD computer-aideddesign (CAD) software according to illustrative embodiments of theinvention uses.

FIG. 12 depicts a flow diagram for a PLD CAD software according to anexemplary embodiment of the invention.

FIG. 13 shows a block diagram of circuitry within a PLD according toexemplary embodiments of the invention to adjust, program, or set thesupply voltage levels of desired parts of the PLD.

FIG. 14 illustrates a circuit arrangement according to exemplaryembodiments of the invention for adjusting supply voltage levels withina PLD in response to an external source.

FIG. 15 depicts a circuit arrangement for adjusting supply voltagelevel(s) within a PLD according to exemplary embodiments of theinvention.

DETAILED DESCRIPTION

The inventive concepts contemplate apparatus and associated methods forPLDs that feature adjustable supply voltage (and, hence, powerconsumption and performance), reduced noise levels, and noise isolation.The inventive concepts help to overcome excessive power density levelsthat conventional PLDs suffer. Moreover, one may adjust the performancelevel of a desired portion, circuit, or block (or all circuits andblocks), of a PLD according to the invention. Put another way, one mayadjust the performance by programming the supply voltage and theattendant power dissipation of the circuitry within the PLD with adesired level of granularity, ranging from individual circuit blocks,all the way to the entire PLD circuitry.

More specifically, and as described below in detail, the inventiveconcepts contemplate controlling the supply voltage and powerconsumption of one or more circuits or blocks of circuits within the PLDby using a variable impedance circuit. In addition, one may use thevariable impedance circuit to form a filter that, simultaneously withthe adjustment of the power consumption, tend to reduce the noise levelspresent within the PLD. The reduced noise levels help to protectsensitive circuitry within the PLD from adverse effects of electricalnoise. Furthermore, one may protect noise-sensitive circuitry within thePLD by using deep n-well structures within the PLD that help to isolatethe sensitive circuitry from sources of electrical noise.

The inventive concepts provide the following benefits over traditionalimplementations. First, they allow trading off performance and powerconsumption or optimizing the performance-power consumption tradeoff.Second, one may selectively set, program, or adjust the supply voltageand power consumption in critical circuit paths or parts of the PLD soas to increase their performance as desired. Conversely, one mayselectively set, program, or adjust the supply voltage and powerconsumption in non-critical circuit paths or parts of the PLD to levelscommensurate with their desired performance.

One may also employ the inventive concepts to prevent (or reduce theprobability of) thermal runaway. More specifically, in a traditionalPLD, circuits operating at relatively high speeds tend to consume morepower, resulting in temperature increase of the PLD. The increased powerconsumption may in turn cause those circuits to consume more power. Thispositive feedback mechanism may increase the power densities to unsafeor destructive levels. In PLDs according to the invention, one mayadjust or control the supply voltage and power consumption levels ofvarious blocks and, hence, reduce the likelihood of thermal runaway.Furthermore, the inventive concepts help to provide better performanceby reducing the noise levels within the PLD and to isolatenoise-sensitive circuitry from the undesirable effects of noise.

FIG. 1 shows a general block diagram of a PLD 103 according to anillustrative embodiment of the invention. PLD 103 includes configurationcircuitry 130, configuration memory 133, control circuitry 136,programmable logic 106, programmable interconnect 109, and I/O circuitry112. In addition, PLD 103 may include test/debug circuitry 115, one ormore processors 118, one or more communication circuitry 121, one ormore memories 124, one or more controllers 127, as desired.

Note that FIG. 1 shows a simplified block diagram of PLD 103. Thus, PLD103 may include other blocks and circuitry, as persons of ordinary skillin the art understand. Examples of such circuitry include clockgeneration and distribution circuits, redundancy circuits, and the like.Furthermore, PLD 103 may include, analog circuitry, other digitalcircuitry, and/or mixed-mode circuitry, as desired.

Programmable logic 106 includes blocks of configurable or programmablelogic circuitry, such as look-up tables (LUTs), product-term logic,multiplexers, logic gates, registers, memory, and the like. Programmableinterconnect 109 couples to programmable logic 106 and providesconfigurable interconnects (coupling mechanisms) between various blockswithin programmable logic 106 and other circuitry within or outside PLD103.

Control circuitry 136 controls various operations within PLD 103. Underthe supervision of control circuitry 136, PLD configuration circuitry130 uses configuration data (which it obtains from an external source,such as a storage device, a host, etc.) to program or configure thefunctionality of PLD 103. The configuration data typically reside inconfiguration memory 133. The configuration data determine thefunctionality of PLD 103 by programming programmable logic 106 andprogrammable interconnect 109, as persons skilled in the art with thebenefit of the description of the invention understand.

I/O circuitry 112 may constitute a wide variety of I/O devices orcircuits, as persons of ordinary skill in the art who have the benefitof the description of the invention understand. I/O circuitry 112 maycouple to various parts of PLD 103, for example, programmable logic 106and programmable interconnect 109. I/O circuitry 112 provides amechanism and circuitry for various blocks within PLD 103 to communicatewith external circuitry or devices.

Test/debug circuitry 115 facilitates the testing and troubleshooting ofvarious blocks and circuits within PLD 103. Test/debug circuitry 115 mayinclude a variety of blocks or circuits known to persons of ordinaryskill in the art who have the benefit of the description of theinvention. For example, test/debug circuitry 115 may include circuitsfor performing tests after PLD 103 powers up or resets, as desired.Test/debug circuitry 115 may also include coding and parity circuits, asdesired.

As noted above, PLD 103 may include one or more processors 118.Processor 118 may couple to other blocks and circuits within PLD 103.Processor 118 may receive data and information from circuits within orexternal to PLD 103 and process the information in a wide variety ofways, as persons skilled in the art with the benefit of the descriptionof the invention appreciate. One or more of processor(s) 118 mayconstitute a digital signal processor (DSP). DSPs allow performing awide variety of signal processing tasks, such as compression,decompression, audio processing, video processing, filtering, and thelike, as desired.

PLD 103 may also include one or more communication circuitry 121.Communication circuitry 121 may facilitate data and information exchangebetween various circuits within PLD 103 and circuits external to PLD103, as persons of ordinary skill in the art who have the benefit of thedescription of the invention understand. As an example, communicationcircuitry 121 may provide various protocol functionality (e.g.,Transmission Control Protocol/Internet Protocol (TCP/IP), User DatagramProtocol (UDP) etc.), as desired. As another example, communicationcircuitry 121 may include network (e.g., Ethernet, token ring, etc.) orbus interface circuitry, as desired.

PLD 103 may further include one or more memories 124 and one or morecontroller(s) 127. Memory 124 allows the storage of various data andinformation (such as user-data, intermediate results, calculationresults, etc.) within PLD 103. Memory 124 may have a granular or blockform, as desired. Controller 127 allows interfacing to, and controllingthe operation and various functions of circuitry outside the PLD. Forexample, controller 127 may constitute a memory controller thatinterfaces to and controls an external synchronous dynamic random accessmemory (SDRAM), as desired.

In addition to the circuitry that FIG. 1 shows, PLD 103 may includeanalog or mixed-mode circuitry 139, sometimes known as analog ormixed-mode intellectual property (IP) blocks. For example, PLD 103 mayinclude amplifiers, digital-to-analog converters, analog-to-digitalconverters, filters, and the like. By their nature, analog/mixed-modecircuits tend to exhibit sensitivity to noise. As described below indetail, the inventive concepts help to isolate noise-sensitive circuitryfrom noise-generating circuitry. Furthermore, the inventive conceptsinclude techniques that tend to reduce the noise levels present in PLDs.

FIG. 2 shows a floor-plan of a PLD 103 according to an exemplaryembodiment of the invention. PLD 103 includes programmable logic 106arranged as a two-dimensional array. Programmable interconnect 109,arranged as horizontal interconnect and vertical interconnect, couplesthe blocks of programmable logic 106 to one another.

One may adjust the supply voltage and, hence, the power dissipationlevel, of each block of programmable logic 106, each segment ofprogrammable interconnect 109, or both, as desired. Furthermore, one mayadjust the supply voltage and the power dissipation level of a portionof one or more blocks of programmable logic 106, a portion ofprogrammable interconnect 109, or both, as desired.

In illustrative embodiments, PLDs according to the invention have ahierarchical architecture. In other words, each block of programmablelogic 106 in FIG. 2 may in turn include smaller or more granularprogrammable logic blocks or circuits. One may adjust the supply voltageand power consumption or dissipation in each level of the hierarchicalarchitecture of the PLD, as desired.

FIG. 3 shows a block diagram of an exemplary embodiment of programmablelogic 106 in a PLD according to the invention. Programmable logic 106includes logic elements or programmable logic circuits 250, localinterconnect 253, interface circuit 256, and interface circuit 259.Logic elements 250 provide configurable or programmable logic functions,for example, LUTs, registers, product-term logic, etc., as persons ofordinary skill in the art who have the benefit of the description of theinvention understand. Local interconnect 253 provides a configurable orprogrammable mechanism for logic elements 250 to couple to one anotheror to programmable interconnect 109 (sometimes called “globalinterconnect”), as desired.

Interface circuit 256 and interface circuit 259 provide a configurableor programmable way for programmable logic 106 block of circuitry tocouple to programmable interconnect 109 (and hence to other programmablelogic 106, as FIG. 2 shows). Interface circuit 256 and interface circuit259 may include multiplexers (MUXs), registers, buffers, drivers, andthe like, as persons of ordinary skill in the art who have the benefitof the description of the invention understand.

One may adjust the supply voltage and power consumption of each portionor block of circuitry within PLD 103 (see FIGS. 1-3), as desired.Furthermore, one may adjust the supply voltage and power consumption ofeach portion or block of circuitry independently of others, on anindividual or collective basis, as desired. Within each portion or blockof circuitry, one may adjust the supply voltage and power consumption ofeach sub-block, or groups of sub-blocks, as desired.

For example, one may adjust the supply voltage and power consumption ofall or a portion of the following circuitry within a PLD according toexemplary embodiments of the invention: one or more of the blocks inFIG. 1 (e.g., programmable logic 106, programmable interconnect 109,etc.); one or more logic elements 250 within one or more programmablelogic blocks 106; one or more interface circuits 256 and/or 259, withinone or more programmable logic blocks 106; one or more localinterconnect within one or more programmable logic 106; and one or moreMUXs, drivers, buffers, etc., within one or more interface circuits 256and/or 259.

As noted above, one may make the supply voltage and power consumptionadjustments in any desired level of granularity. In other words, one maymake the adjustments applicable to sub-blocks, blocks, regions, or theentire PLD, as desired, and as applicable. For example, one may makesupply voltage and power consumption adjustments to one or more of suchelements of the PLD independently of one or more of other elementswithin the PLD, as desired. As persons of ordinary skill in the art withthe benefit of the description of the invention understand, one mayadjust the supply voltage and power consumption of some parts of a PLDand yet provide a fixed or default supply voltage and power consumptionfor other parts of the PLD, as desired.

FIG. 4 shows a circuit arrangement for adjusting the supply voltage and,hence, the power consumption of a desired circuit in a PLD according toan exemplary embodiment of the invention. More specifically, the circuitarrangement in FIG. 4 shows a controlled PLD circuit 300 that includescontrol circuit 303, PLD circuit 306, and variable impedance device 309.

The circuit operates as follows: In response to one or more signals notshown explicitly in FIG. 4 (such as a bias signal and configurationsignals, described in connection with FIG. 13) circuit 303 applies acorresponding control signal (or signals, depending on the nature ofvariable impedance device 309) so as to cause adjustment of the supplyvoltage that variable impedance device 309 provides to PLD circuit 306.Consequently, control circuit 303 can cause the adjustment of the powerconsumption (and other performance criteria, such as operating speed) ofPLD circuit 306.

Variable impedance device 309 couples the supply voltage, V_(DD), to PLDcircuit 306. When variable impedance device 309 has a relatively highimpedance, PLD circuit 306 conducts relatively little current, and has anearly zero supply voltage. Thus, PLD circuit 306 effectively shuts downor enters an OFF state or sleep mode. In this state, PLD circuit 306consumes nearly zero power.

At the other extreme, when variable impedance device 309 has arelatively low impedance, PLD circuit 306 receives nearly the voltageV_(DD) as its supply voltage (minus any drop across variable impedancedevice 309). In this state, PLD circuit 306 typically has higher powerconsumption, but also higher speed. Thus, by varying the effectivesupply voltage of PLD circuit 306 between the two extremes of near-zeroand near-VDD supply voltages, one may trade off its various performancemeasures, such as power consumption and speed.

PLD circuit 306 may constitute any desired region, block, circuitry,sub-block, or collection of each of those parts, of a PLD. For example,PLD circuit 306 may constitute one or more of the elements shown inFIGS. 1-3, such as programmable interconnect 109, logic elements 250,etc., as desired.

As described below in detail, control circuit 303 may operate under thesupervision of one or more other parts of the PLD, or under the controlof an external source, or a combination of internal and externalsources, as desired. Control circuit 303 causes the impedance of thevariable impedance device to change. As a result, the effective supplyvoltage provided to PLD circuit 306 varies. The effective supply voltageof PLD circuit 306 affects its characteristics, such as operating speed,power consumption, and the like. By adjusting the supply voltage levelfor PLD circuit 306, one may trade off its various characteristics, suchas speed versus power consumption.

Variable impedance device 309 may constitute a desired type of device,depending on factors such as the particular PLD implementation, circuitand process technology, and the like, as persons of ordinary skill inthe art who have the benefit of the description of the inventionunderstand. As one example, variable impedance device 309 may constitutea transistor.

FIG. 5 illustrates another circuit arrangement for adjusting the supplyvoltage of a desired circuit in a PLD according to an exemplaryembodiment of the invention. The circuit arrangement in FIG. 5 issimilar to the circuit in FIG. 4. FIG. 5, however, uses a transistor 320and, more particularly, a metal oxide semiconductor field effecttransistor (MOSFET) transistor, as a particular type of variableimpedance device.

Depending on factors such as the particular PLD implementation, circuitand process technology, and the like, as persons of ordinary skill inthe art who have the benefit of the description of the inventionunderstand, transistor 320 may constitute a variety of devices, such asbipolar junction transistors (BJTs), bipolar hetero-junction transistor(BHT), and the like.

In one embodiment implemented using metal oxide semiconductor (MOS) orcomplementary MOS (CMOS) technology, transistor 320 may constitute anative transistor, as desired. Native transistors may have a negative orsmall threshold voltage, V_(T), thus making biasing or drivingtransistor 320 easier in situations where a relatively small V_(DD)results in a small headroom in the output voltage of control circuit303.

As noted above, PLDs according to the invention may includenoise-sensitive analog or mixed-mode circuitry. One may use filteringtechniques to help reduce the overall noise in the PLD or the noiselevel that the analog or mixed-mode circuitry experiences.

FIG. 6 depicts a circuit arrangement for reducing the noise level in aPLD according to an exemplary embodiment of the invention. ControlledPLD circuit 300 in FIG. 6 is analogous to the circuit shown in FIG. 4,and provides similar benefits. Thus, the circuitry in FIG. 6 providesthe capability of controlling the supply voltage and, hence, theperformance, of PLD circuit 306, as described above in detail. In thecircuit of FIG. 6, PLD circuit 306 constitutes a circuit with relativelyhigh sensitivity to noise, such as an analog or mixed-mode circuit.

In addition to the elements shown in FIG. 4, the circuit arrangement inFIG. 6 includes capacitor 323 and capacitor 326. Together with variousimpedances present in the circuit, each of those capacitors forms afilter. For example, capacitor 326, together with the parallel impedanceof variable impedance device 309 and PLD circuit 306, forms a low-passfilter. By filtering higher frequencies, the low-pass filters tend toreduce the overall noise level that PLD circuit 306 experiences. Notethat one may omit one of capacitors 323 and 326, depending on factorssuch as the desired level of filtering, the size and value ofcomponents, and the like, as persons of ordinary skill in the art whohave the benefit of the description of the invention understand.

FIG. 7 shows another circuit arrangement for reducing the noise level ina PLD according to an exemplary embodiment of the invention. The circuitarrangement in FIG. 7 constitutes a more specific implementation of thecircuit in FIG. 6. More specifically, rather than a general variableimpedance device 309 in FIG. 6, the circuit arrangement in FIG. 7 usestransistor 320. Transistor 320 may generally constitute any of thedevices described above with respect to FIG. 5, as desired. Note that,as described above, one may omit one of capacitors 323 and 326,depending on factors such as the desired level of filtering, the sizeand value of components, and the like, as persons of ordinary skill inthe art who have the benefit of the description of the inventionunderstand.

Using controlled PLD circuit 300 described above, one may adjust thesupply voltage and power consumption and thus performance of variousparts of PLDs. FIG. 8 shows an arrangement for providing a flexiblemechanism for adjusting the performance of the various parts of a PLD103 according to an exemplary embodiment of the invention. PLD 103includes one or more PLD circuit regions or “islands” 400A-400C. EachPLD circuit region 400A-400C includes one or more controlled PLDcircuits 300, as described above.

Each of PLD circuit regions 400A-400C may receive one or more powersupply voltages, labeled as V_(DD1)-V_(DDN). As examples, PLD circuitregion 400A receives V_(DD1), whereas circuit region 400B receivesV_(DD1)-V_(DD3), and circuit region 400C receives V_(DDN). Each ofcontrolled PLD circuits 300 can adjust the supply voltage provided toits respective PLD circuit 306 (see, for example, FIG. 4), as describedabove in detail.

By assigning a desired set of power supply voltages to each of PLDcircuit regions 400A-400C, one may adjust the supply voltage and powerconsumption of circuitry within the circuit regions. Furthermore, byincluding a desired set of controlled PLD circuits 300 within a givencircuit region 400A-400C, one may match the type of supply voltageadjustment in each circuit region 40OA-400C with one or more suitablecontrolled PLD circuits 300. Thus, the arrangement in FIG. 8 provides aflexible mechanism for allocating various PLD resources to implementingan appropriate part of the user's design or system so as to provide anefficient implementation with improved performance adjustmentcapabilities and better overall performance. (e.g., speed-powerconsumption tradeoff).

Note that, in addition to, or rather than, receiving external powersupply voltages (e.g., V_(DD1)-V_(DDN) in FIG. 8), PLD 103 may generatepower supply voltages internally, as desired. FIGS. 9A-9C show circuitarrangements for distributing and generating power supply voltages inPLDs according to exemplary embodiments of the invention.

In FIG. 9A, PLD 103 simply uses the external power supply voltages thatit receives, e.g., V_(DD1)-V_(DDN). In this scenario, PLD 103 may use apower distribution and supply voltage adjustment scheme, such as thearrangement in FIG. 8.

In FIG. 9B, PLD 103 receives power supply voltages V_(DD1)-V_(DDN). PLD103 may regulate one or more of the power supply voltages to generateone or more internal power supply voltages. PLD 103 may then use theexternal and the internally generated powers supply voltages in a powerdistribution and supply voltage adjustment scheme, e.g., as shown inFIG. 8. In the particular example shown, PLD 103 uses voltage regulator450 to generate internal power supply voltage V_(DD2)′ from externalpower supply voltage V_(DD2).

In FIG. 9C, PLD 103 receives power supply voltages V_(DD1)-V_(DDN). PLD103 may use one or more charge pumps 453 to generate one or moreinternal power supply voltages. PLD 103 may then use the external andthe internally generated powers supply voltages in a power distributionand supply voltage adjustment scheme, e.g., as shown in FIG. 8. In theparticular example shown, PLD 103 uses charge pump 453 to generateinternal power supply voltage V_(DD1)′ from external power supplyvoltage V_(DD1). Internal power supply voltage V_(DD1)′ has a highervoltage level than V_(DD1).

As noted above, the inventive concepts include techniques for isolatingnoise-sensitive circuits from noise-generating circuitry with the PLD.More particularly, in PLDs fabricated using CMOS technology, various PLDcircuits typically reside in a number of deep n-wells. By strategicallyplacing noise-sensitive circuits in isolated n-wells, one may shield orisolate the noise-sensitive circuits from sources of noise. Thus, onemay provide islands within the PLD, each with its own supply voltage,power consumption, noise generation, and noise isolationcharacteristics. The islands provide a mechanism in PLDs according tothe invention for providing a flexible implementation of a user's designor system.

FIG. 10 shows an example of using n-wells to isolate noise-sensitivecircuits in a PLD according to an illustrative embodiment of theinvention. The PLD resides in substrate 500. Substrate 500 includes deepn-wells 503, 506, and 509. Each of deep n-wells 503, 506, and 509 mayinclude a variety of PLD circuitry, such as the circuits shown in FIGS.1-3.

As noted, one may place the various circuits in deep n-wells 503, 506,and 509 so as to reduce interference and noise. For example, one mayplace circuitry with relatively high noise sensitivity (labeled as 506A)in a PLD that includes circuits that generate moderate amounts of noise(labeled as 506B) as well as circuits that produce relatively highlevels of noise (labeled as 506C). As the example in FIG. 10illustrates, one may place circuits 506A, 506B, and 506C in deep n-wells503, 506, and 509, respectively. Noise and interference tends todecrease by the virtue of placing noise-sensitive circuit 506A farthestfrom the relatively high levels of noise that circuit 506C generates,but nearer to the moderate levels of noise that circuit 506B produces.

Note that deep n-wells represent an illustrative construct in a PLDfabrication technology. Depending on a number of factors, one may useother constructs and devices in current and future fabricationtechnologies, as persons of ordinary skill in the art who have thebenefit of the description of the invention understand. The factorsinclude the type and characteristics of the technology and the devicesand constructs available, the desired design and performancespecifications, cost, complexity, area efficiency, and the like.

As an example, one may use silicon-on-insulator (SOI) technology toprovide noise isolation and control within PLDs. More specifically, andas persons of ordinary skill in the art who have the benefit of thedescription of the invention understand, SOI circuits tend to provideisolation between transistors because of the insulator layer (typicallysilicon dioxide). Thus, SOI circuits provide a mechanism for isolatingnoise-sensitive circuits from noise-generating circuits of the PLD.

As noted above, the user may adjust the supply voltage and powerconsumption and noise exposure or performance of various portions ofPLDs according to the invention. The user may do so by using thesoftware used to map a design to a PLD. FIG. 11 depicts various softwaremodules that PLD computer-aided design (CAD) software according toillustrative embodiments of the invention uses. The modules includedesign-entry module 550, synthesis module 553, place-and-route module556, and verification module 559.

Design-entry module 550 allows the integration of multiple design files.The user may generate the design files by using design-entry module 550or by using a variety of electronic design automation (EDA) or CAD tools(such as industry-standard EDA tools), as desired. The user may enterthe design in a graphic format, a waveform-based format, a schematicformat, in a text or binary format, or as a combination of thoseformats, as desired.

Synthesis module 553 accepts the output of design-entry module 550.Based on the user-provided design, synthesis module 553 generatesappropriate logic circuitry that realizes the user-provided design. Oneor more PLDs (not shown explicitly) implement the synthesized overalldesign or system.

Synthesis module 553 may also generate any glue logic that allowsintegration and proper operation and interfacing of various modules inthe user's designs. For example, synthesis module 553 providesappropriate hardware so that an output of one block properly interfaceswith an input of another block. Synthesis module 553 may provideappropriate hardware so as to meet the specifications of each of themodules in the overall design or system.

Furthermore, synthesis module 553 may include algorithms and routinesfor optimizing the synthesized design. Through optimization, synthesismodule 553 seeks to more efficiently use the resources of the one ormore PLDs that implement the overall design or system. In someembodiments, synthesis module 553 may identify critical paths within thesynthesized design or system. Synthesis module 553 provides its outputto place-and-route module 556.

Place-and-route module 556 uses the designer's timing specifications toperform optimal logic mapping and placement. The logic mapping andplacement determine the use of routing resources within the PLD(s). Inother words, by use of particular programmable interconnects with thePLD(s) for certain parts of the design, place-and-route module 556 helpsoptimize the performance of the overall design or system.

By proper use of PLD routing resources, place-and-route module 556 helpsto meet the critical timing paths of the overall design or system.Place-and-route module 556 optimizes the critical timing paths to helpprovides timing closure faster in a manner known to persons of ordinaryskill in the art with the benefit of the description of the invention.As a result, the overall design or system can achieve faster performance(i.e., operate at a higher clock rate or have higher throughput).

Furthermore, place-and-route module 556 adjusts the supply voltage andpower consumption and the noise performance or exposure of a portion ofor all of the PLD(s) that implement the design or system.Place-and-route module 556 may do so automatically, according touser-specified criteria, or a combination of the two. Place-and-routemodule 556 may use the user-specified criteria (for example, performancespecifications, such as power dissipation, noise exposure orperformance, speed, and/or current-drive capability). In addition, orinstead, place-and-route module 556 may use the information aboutcritical paths within the design or system to adjust the supplyvoltage(s), physical placement so as to reduce noise generation andexposure, and power consumption of parts or all of the design or system,as desired.

For example, place-and-route module 556 may adjust the supply voltageand power consumption of the critical parts of the design or system soas to achieve higher performance. Place-and-route module 556 may takeinto account power dissipation criteria (e.g., maximum power density) soas to trade off power and performance, as desired. Place-and-routemodule 556 provides the optimized design to verification module 559.

Verification module 559 performs simulation and verification of thedesign. The simulation and verification seek in part to verify that thedesign complies with the user's prescribed specifications. Thesimulation and verification also aim at detecting and correcting anydesign problems before prototyping the design. Thus, verification module559 helps the user to reduce the overall cost and time-to-market of theoverall design or system.

Verification module 559 may support and perform a variety ofverification and simulation options, as desired. The options may includedesign-rule checking, functional verification, test-bench generation,static timing analysis, timing simulation, hardware/software simulation,in-system verification, board-level timing analysis, signal integrityanalysis and electromagnetic compatibility (EMC), formal netlistverification, noise generation and exposure, and power-consumptionestimation, as desired. Note that one may perform other or additionalverification techniques as desired and as persons of ordinary skill inthe art who have the benefit of the description of the inventionunderstand.

FIG. 12 illustrates a flow diagram for a PLD CAD software according toan exemplary embodiment of the invention. The PLD CAD shown in FIG. 12incorporates the choice of supply voltage and power consumption for eachregion of the PLD into a timing-driven place-and-route CAD system. Notethat, as desired, one may include criteria for noise generation, noiseexposure, and/or noise isolation into the PLD CAD in FIG. 12 by makingmodifications that fall within the knowledge of persons of ordinaryskill in the art who have the benefit of the description of theinvention.

Starting the process, at 603 the PLD CAD sets initial supply voltagelevels (corresponding to estimated power consumption levels). At 606 thesoftware generates an initial placement. Then, at 609 it analyzes thetiming of the circuitry using delay estimates that reflect the varioussettings, such as supply voltage settings. At 612 the softwaredetermines whether it has met the user's various criteria, such astiming and power goals. If so, at 615 it records the placement andsupply voltage selections. If not, the software checks at 618 todetermine whether it has reached the iteration limit. If so, it proceedsto 615 to record the current placement and supply voltage selections.

If the software has not reached the iteration limit, it increments theiteration count (not shown explicitly), and at 621 changes the settingsof at least some regions, circuits, blocks, or parts of the PLD. At 624it analyzes the timing of the circuitry using delay estimates thatreflect the changed settings. At 356 it improves the placement of thecircuit, and jumps to 612 to determine whether it has met the user'stiming and power goals. Once the PLD CAD has implemented a design (i.e.,synthesized, placed and routed the design), the CAD software shouldautomatically provide data for programming the PLD that set the supplyvoltages of various parts of the PLD.

FIG. 13 shows a block diagram of circuitry within a PLD according toexemplary embodiments of the invention to adjust, program, or set thesupply voltage levels of desired parts of the PLD. The circuitryincludes bias circuit 703, a plurality of configuration memory(configuration random-access memory, or CRAM, or other implementationsof the memory) cells 709, and controlled PLD circuits 300.

Bias circuit 703 generates one or more signals 706 and provides thosesignal(s) to controlled PLD circuits 300 (more particularly, to controlcircuit 303, as shown, for example, in FIG. 4). In other word, biascircuit 703 provides one or more global bias signals to controlled PLDcircuits 300. Furthermore, each of CRAM cells 709 provides to arespective one of controlled PLD circuits 300 (more particularly, tocontrol circuit 303). The signals from CRAM cells 709 representconfiguration data for the various circuits within the PLD, as providedby the PLD CAD program described above. In response to configurationdata from CRAM cells 709, the control circuit (not shown explicitly) ineach of controlled PLD circuits 300 generates one or more signals tocontrol the impedance of the variable impedance device (not shownexplicitly) as a function of signal(s) 706.

In other variations, each of CRAM cells 709 may provide configurationdata to more than one controlled PLD circuit, as desired. Conversely,one may modify the control circuit within controlled PLD circuits 300 soas to make it responsive to configuration data from more than one CRAMcell 709, as desired.

Note that one may adjust, program, or set supply voltage levels inresponse to sources external to the PLD. For example, one maycommunicate supply voltage levels to a PLD to adjust or modify itsperformance. FIG. 14 shows a circuit arrangement according to exemplaryembodiments of the invention for adjusting supply voltage levels withinPLD 103 in response to an external source 753. The circuit arrangementincludes external source 753, communication/interface circuit 762, andbias circuit 703 (see FIG. 13).

Communication/interface circuit 762 provides a mechanism for externalsource 753 and bias circuit 703 to communicate and exchange information.External source 753 may provide one or more control signal(s) 756 tocommunication/interface circuit 762 within PLD 103.Communication/interface circuit 762 provides the information receivedfrom external source 753 to bias circuit 703. In response, bias circuit703 generates one or more signals 706, with levels corresponding tocontrol signal(s) 756. Communication/interface circuit 762 may provideinformation, such as status signals, from bias circuit 703 (or PLD 103generally) to external source 753.

External source 753 may constitute a variety of devices, structures, orarrangements, as persons of ordinary skill in the art with the benefitof the description of the invention understand. For example, externalsource 753 may constitute a computer network (e.g., the Internet), atelephone-line communication link, a wireless communication link, a bus,etc., as desired.

Note that one may adjust, program, or set the supply voltage levels inPLDs on a dynamic or time-varying basis, as desired, to take intoaccount or respond to changing conditions (for example, changes inperformance specifications). As one example, referring to FIG. 14,external source 753 may update or modify control signal(s) 756 that itprovides to PLD 103. Bias circuit 703 responds accordingly to theupdated or modified signal(s) 756.

As another example, one may change or adjust supply levels in responseto changes within PLD 103 itself, for instance, a change in temperature,noise, power consumption, and the like, in one or more circuits or areasof PLD 103. FIG. 15 shows a circuit arrangement for modifying supplyvoltage level(s) within a PLD according to exemplary embodiments of theinvention.

The circuit arrangement includes one or more sensor(s) 803, one or morereference source(s) 806, subtracter 818, and bias circuit 703. Sensor(s)803 sense a desired parameter (e.g., temperature, noise, etc.) in one ormore areas, circuits, or blocks within PLD 103 and provide signal(s) 809to subtracter 818. Reference source(s) 806 provide reference signal(s)812 to subtracter 818. Reference signal(s) 812 may have values thatcorrespond to various levels of the sensed parameter.

Subtracter 818 subtracts reference signal(s) 812 from signal(s) 809 andprovides difference signal(s) 815 to bias circuit 703. Differencesignal(s) 815 may constitute the difference between actual sensedvalue(s) and the desired value(s) in one or more parts of PLD 103. Inresponse to difference signal(s) 815, bias circuit 703 generatessignal(s) 706 (see also FIG. 13).

Bias circuit 703 may use difference signal(s) 815 to generate signal(s)706 that ultimately affect various aspects of the performance of PLD103. For example, if difference signal(s) 815 indicate a lower sensedvalue (say, speed) than a threshold or maximum value, bias circuit 703may generate signal(s) that increase supply voltage level(s) to increaseoperating speed of the desired parts of PLD 103. In contrast, ifdifference signal(s) 815 indicate a sensed level higher than a safe ormaximum level, bias circuit 703 may generate signal(s) that decreasesupply voltage level(s) to safe or desired levels (albeit with adecreased resulting speed).

More generally, one may implement a feedback loop that generates supplyvoltage level(s) so as to target specific performance criteria. Putanother way, one may compare actual performance measures of a PLD todesired or specified measures or criteria and adjust, program, or setsupply voltage levels accordingly.

Note that one may apply the inventive concepts effectively to variousprogrammable logic circuitry or ICs known by other names in the art, asdesired, and as persons skilled in the art with the benefit of thedescription of the invention understand. Such circuitry include devicesknown as complex programmable logic device (CPLD), programmable gatearray (PGA), and field programmable gate array (FPGA).

Referring to the figures, persons of ordinary skill in the art will notethat the various blocks shown may depict mainly the conceptual functionsand signal flow. The actual circuit implementation may or may notcontain separately identifiable hardware for the various functionalblocks and may or may not use the particular circuitry shown. Forexample, one may combine the functionality of various blocks into onecircuit block, as desired. Furthermore, one may realize thefunctionality of a single block in several circuit blocks, as desired.The choice of circuit implementation depends on various factors, such asparticular design and performance specifications for a givenimplementation, as persons of ordinary skill in the art who have thebenefit of the description of the invention understand. Othermodifications and alternative embodiments of the invention in additionto those described here will be apparent to persons of ordinary skill inthe art who have the benefit of the description of the invention.Accordingly, this description teaches those skilled in the art themanner of carrying out the invention and are to be construed asillustrative only.

The forms of the invention shown and described should be taken as thepresently preferred or illustrative embodiments. Persons skilled in theart may make various changes in the shape, size and arrangement of partswithout departing from the scope of the invention described in thisdocument. For example, persons skilled in the art may substituteequivalent elements for the elements illustrated and described here.Moreover, persons skilled in the art who have the benefit of thisdescription of the invention may use certain features of the inventionindependently of the use of other features, without departing from thescope of the invention.

1. A programmable logic device (PLD), comprising a first circuitconfigured to control a supply voltage of a second circuit, the firstcircuit further configured to filter noise within the programmable logicdevice (PLD).
 2. The programmable logic device (PLD) according to claim1, wherein the first circuit comprises a variable impedance device, thevariable impedance device configured to provide the supply voltage ofthe second circuit.
 3. The programmable logic device (PLD) according toclaim 1, wherein the transistor comprises a native transistor of theprogrammable logic device.
 4. The programmable logic device (PLD)according to claim 2, wherein the variable impedance device is furtherconfigured to provide the supply voltage of the second circuit inresponse to a programmable logic device (PLD) configuration datum. 5.The programmable logic device (PLD) according to claim 2, wherein thevariable impedance device comprises a transistor.
 6. The programmablelogic device (PLD) according to claim 3, wherein the first circuitfurther comprises a control circuit coupled to a gate terminal of thetransistor.
 7. The programmable logic device (PLD) according to claim 6,wherein the transistor adjusts the supply voltage of the second circuitin response to an output signal of the control circuit.
 8. Theprogrammable logic device (PLD) according to claim 4, wherein the firstcircuit further comprises a first capacitor coupled to a gate terminalof the transistor.
 9. The programmable logic device (PLD) according toclaim 4, wherein the first circuit further comprises a second capacitorcoupled to a source terminal of the transistor.
 10. The programmablelogic device (PLD) according to claim 7, wherein the output signal ofthe control circuit is derived from information received from aninformation source external to the programmable logic device (PLD). 11.The programmable logic device (PLD) according to claim 6, wherein theoutput signal of the control circuit depends on a power consumption of acircuit within the programmable logic device (PLD).
 12. The programmablelogic device (PLD) according to claim 1, wherein the second circuitcomprises a programmable logic circuit.
 13. The programmable logicdevice (PLD) according to claim 12, wherein the programmable logiccircuit comprises one of a plurality of programmable logic circuitsarranged as a two-dimensional array.
 14. The programmable logic device(PLD) according to claim 12, wherein the programmable logic circuitcomprises a logic element.
 15. The programmable logic device (PLD)according to claim 14, wherein the programmable logic circuit compriseslocal interconnect circuitry.
 16. The programmable logic device (PLD)according to claim 1, wherein the second circuit comprises programmableinterconnect circuitry.
 17. The programmable logic device (PLD)according to claim 1, wherein the second circuit comprises configurationmemory configured to store configuration data of the programmable logicdevice (PLD).
 18. A programmable logic device (PLD), comprising: a firstcircuit, the first circuit residing in a first deep n-well; and a firstvariable impedance device coupled to the first circuit, the firstvariable impedance device configured to adjust a supply voltage of thefirst circuit.
 19. The programmable logic device (PLD) according toclaim 18, further comprising a first capacitor coupled to the firstvariable impedance device.
 20. The programmable logic device (PLD)according to claim 18, comprising: a second circuit, the second circuitresiding in a second deep n-well; and a second variable impedance devicecoupled to the second circuit, the second variable impedance deviceconfigured to adjust a supply voltage of the second circuit.
 21. Theprogrammable logic device (PLD) according to claim 20, furthercomprising a second capacitor coupled to the second variable impedancedevice.
 22. The programmable logic device (PLD) according to claim 20,wherein the first circuit is relatively sensitive to noise.
 23. Theprogrammable logic device (PLD) according to claim 20, wherein the firstcircuit comprises analog circuitry.
 24. The programmable logic device(PLD) according to claim 20, wherein the first circuit comprisesmixed-mode circuitry.
 25. The programmable logic device (PLD) accordingto claim 22, wherein the second circuit generates relatively high levelsof noise.
 26. The programmable logic device (PLD) according to claim 20,wherein the first variable impedance device derives the supply voltageof the first circuit from a first voltage supplied to the programmablelogic device (PLD).
 27. The programmable logic device (PLD) according toclaim 20, wherein the first variable impedance device derives the supplyvoltage of the first circuit from a first voltage, wherein the firstvoltage is derived within the programmable logic device (PLD) from asecond voltage supplied to the programmable logic device (PLD).
 28. Amethod of configuring a programmable logic device (PLD) to implement anelectronic circuit, the method comprising: mapping the electroniccircuit to functional resources within the programmable logic device(PLD) to generate a circuit to be implemented by the programmable logicdevice (PLD); identifying at least one critical circuit path in thecircuit to be implemented by the programmable logic device (PLD); andsetting a supply voltage level of at least a portion of the criticalcircuit path.
 29. The method according to claim 28, wherein setting asupply voltage level of at least a portion of the critical circuit pathfurther comprises programming a configuration memory (CRAM) of theprogrammable logic device (PLD).
 30. The method according to claim 29,wherein setting a supply voltage level of at least a portion of thecritical circuit path further comprises adjusting an impedance of avariable impedance device depending on a value programmed in theconfiguration memory (CRAM).
 31. The method according to claim 28,further comprising adjusting the supply voltage level of at least aportion of the critical circuit path.
 32. The method according to claim31, wherein adjusting the supply voltage level of at least a portion ofthe critical circuit path further comprises trading off speed and powerconsumption of the at least a portion of the critical circuit path. 33.The method according to claim 28, wherein setting a supply voltage levelof at least a portion of the critical circuit path further comprisesusing an output signal of a control circuit.
 34. The method according toclaim 33, wherein setting a supply voltage level of at least a portionof the critical path further comprises adjusting an impedance of avariable impedance device by using the output signal of the controlcircuit.
 35. A method of operating a programmable logic device (PLD),the method comprising: setting a supply voltage level of a first circuitin the programmable logic device (PLD) to a first level; determiningwhether a performance measure of the programmable logic device (PLD)meets a criterion; and adjusting the supply voltage level of the firstcircuit depending on whether the performance measure of the programmablelogic device (PLD) meets the criterion.
 36. The method according toclaim 35, wherein determining whether a performance measure of theprogrammable logic device (PLD) meets a criterion further comprisesobtaining the performance measure.
 37. The method according to claim 36,wherein obtaining the performance measure further comprises sensing aquantity within the programmable logic device (PLD).
 38. The methodaccording to claim 37, wherein sensing a quantity within theprogrammable logic device (PLD) further comprises sensing a temperature.39. The method according to claim 35, wherein adjusting the supplyvoltage level of the first circuit further comprises: leaving the supplyvoltage level of the first circuit unchanged if the performance measureof the programmable logic device (PLD) meets the criterion; and changingthe supply voltage level of the first circuit to a second level if theperformance measure of the programmable logic device (PLD) fails to meetthe criterion.
 40. The method according to claim 35, wherein theperformance measure comprises a speed of operation of the first circuit.41. The method according to claim 35, wherein the performance measurecomprises a power consumption of the first circuit.
 42. The methodaccording to claim 35, wherein setting a supply voltage level of a firstcircuit in the programmable logic device (PLD) to a first level furthercomprises setting the supply voltage to a level derived from informationreceived from a source external to the programmable logic device. 43.The method according to claim 35, wherein setting a supply voltage levelof a first circuit in the programmable logic device (PLD) to a firstlevel further comprises setting the supply voltage to a level specifiedby configuration data of the programmable logic device (PLD).
 44. Themethod according to claim 35, further comprising using a feedbackcircuit to determine if the performance measure of the programmablelogic device (PLD) meets the criterion.
 45. A method of operating aprogrammable logic device (PLD) configured to function in an operatingenvironment, the method comprising: setting a supply voltage level of afirst circuit in the programmable logic device (PLD) to a first level;and adjusting the supply voltage level of the first circuit depending onat least one characteristic of the operating environment of theprogrammable logic device (PLD).
 46. The method according to claim 45,wherein adjusting the supply voltage level of the first circuit furthercomprises adjusting the supply voltage level of the first circuit to asecond level if the at least one characteristic of the operatingenvironment indicates that a performance of the first circuit should bechanged.
 47. The method according to claim 46, wherein adjusting thesupply voltage level of the first circuit further comprises increasingan operating speed of the first circuit if the at least onecharacteristic of the operating environment indicates that a performanceof the first circuit should be increased.
 48. The method according toclaim 47, wherein adjusting the supply voltage level of the firstcircuit further comprises trading off the operating speed of the firstcircuit with a power consumption of the first circuit.
 49. The methodaccording to claim 46, wherein adjusting the body-bias level of the atleast one transistor further comprises decreasing an operating speed ofthe first circuit if the at least one characteristic of the operatingenvironment indicates that a performance of the first circuit should bedecreased.